The present invention relates to a method and/or architecture for implementing programmable interconnect matrices (PIMs) that contain two or more stages generally and, more particularly, to a method and/or architecture for implementing a PIM that equalizes the delay in stage-to-stage routing.
Referring to FIG. 1, a conventional programmable interconnect matrix (PIM) 10 is shown. The PIM 10 includes a first stage 12 and a second stage 14. The first stage 12 has a number of multiplexers 16a-16n. The second stage 14 has a number of multiplexers 18a-18n. An output of the multiplexers 16a-16n is used as an input to the multiplexers 18a-18n. The conventional configuration results in routes of different length connecting the first stage 12 and the second stage 14. The different lengths of the individual routes result in different delays, depending on the path taken through the PIM 10. With the conventional configuration, the lengths of the individual routes connecting the first stage 12 to the second stage 14 are different. Therefore, the delays are difficult, if not impossible, to equalize. The propagation delay through the worst case path of the PIM 10 sets the overall delay specification for all paths. Additionally, connections from stage-to-stage can become congested. Reducing or eliminating the congestion can require routing outside the multiplexer bounding box.
The present invention concerns an apparatus comprising a first stage and a second stage. The first stage may comprise a first section and a second section. The second stage may be embedded between the first and second sections. The first and second stages may be configured to equalize signal paths between a plurality of inputs of the first stage and a plurality of outputs of the second stage.
The objects, features and advantages of the present invention include providing an architecture for implementing programmable interconnect matrices containing two or more stages That may (i) optimize path delays, (ii) allow different paths to have relatively the same delay, (iii) equalize the delay in the stage-to-stage routing, and/or (iv) configure routing lengths (e.g., horizontal, vertical, etc.) to equalize overall path delay.